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TCN75
2-Wire Serial Temperature Sensor and Thermal Monitor
Features:
* Solid-State Temperature Sensing: 0.5C Accuracy (Typ.) * Operates from -55C to +125C * Operating Supply Range: 2.7V to 5.5V * Programmable Trip Point and Hysteresis with Power-up Defaults * Standard 2-Wire Serial Interface * Thermal Event Alarm Output Functions as Interrupt or Comparator/Thermostat Output * Up to 8 TCN75s may Share the Same Bus * Shutdown Mode for Low Standby Power Consumption * 5V Tolerant I/O at VDD = 3V * Low Power: - 250 A (Typ.) Operating - 1 A (Typ.) Shutdown Mode * 8-Pin SOIC and MSOP Packaging
Package Type
SOIC
SDA SCL INT/CMPTR GND 1 2 3 4 8 VDD A0 A1 A2
TCN75MOA
7 6 5
MSOP
SDA 1 SCL 2 INT/CMPTR 3 GND 4 8 VDD A0 A1 A2
TCN75MUA
7 6 5
General Description: Applications:
* * * * Thermal Protection for High-Performance CPUs Solid-State Thermometer Fire/Heat Alarms Thermal Management in Electronic Systems: - Computers - Telecom Racks - Power Supplies/UPS/Amplifiers * Copiers/Office Electronics * Consumer Electronics * Process Control The TCN75 is a serially programmable temperature sensor that notifies the host controller when ambient temperature exceeds a user programmed set point. Hysteresis is also programmable. The INT/CMPTR output is programmable as either a simple comparator for thermostat operation or as a temperature event interrupt. Communication with the TCN75 is accomplished via a two-wire bus that is compatible with industry standard protocols. This permits reading the current temperature, programming the set point and hysteresis, and configuring the device. The TCN75 powers up in Comparator mode with a default set point of 80C with 5C hysteresis. Defaults allow independent operation as a stand-alone thermostat. A shutdown command may be sent via the 2-wire bus to activate the low-power Standby mode. Address selection inputs allow up to eight TCN75s to share the same 2-wire bus for multizone monitoring. All registers can be read by the host and the INT/ CMPTR output's polarity is user programmable. Both polled and interrupt driven systems are easily accommodated. Small physical size, low installed cost, and ease-of-use make the TCN75 an ideal choice for implementing sophisticated system management schemes.
(c) 2006 Microchip Technology Inc.
DS21490C-page 1
TCN75
Device Selection Table
Part Number TCN75-3.3MOA TCN75-5.0MOA TCN75-3.3MUA TCN75-5.0MUA Supply Voltage 3.3 5.0 3.3 5.0 Package 8-Pin SOIC 8-Pin SOIC 8-Pin MSOP 8-PIn MSOP Junction Temperature Range -55C to +125C -55C to +125C -55C to +125C -55C to +125C
Functional Block Diagram
TCN75
9-Bit DS A/D Converter Temp Sensor Control Logic INT/CMPTR
VDD
Register Set Configuration Temperature TSET THYST
SDA SCL A0 A1 A2 Two Wire Serial Port Interface
DS21490C-page 2
(c) 2006 Microchip Technology Inc.
TCN75
1.0 ELECTRICAL CHARACTERISTICS
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings*
Supply Voltage (VDD) ............................................ 6.0V ESD Susceptibility (Note 3) ............................... 1000V Voltage on Pins: A0, A1, A2 .......... (GND - 0.3V) to (VDD + 0.3V) Voltage on Pins: SDA, SCL, INT/CMPTR .. (GND - 0.3V) to 5.5V Thermal Resistance (Junction to Ambient) 8-Pin SOIC.......................................... 170C/W 8-Pin MSOP ....................................... 250C//W Operating Temperature Range (TJ): -55C to +125C Storage Temperature Range (TSTG): -65C to +150C
TCN75 ELECTRICAL SPECIFICATIONS
Electrical Characteristics: VDD = 2.7V - 5.5V, -55C (TA = TJ) 125C, unless otherwise noted. Symbol Power Supply VDD IDD IDD1 Power Supply Voltage Operating Current Standby Supply Current 2.7 -- -- -- -- 0.250 -- 1 5.5 -- 1.0 -- -- mA A Serial Port Inactive (TA = TJ = 25C) Serial Port Active Shutdown Mode, Serial Port Inactive (TA = TJ = 25C) Parameter Min Typ Max Units Test Conditions
INT/CMPTR Output IOL tTRIP VOL T Sink Current: INT/CMPTR, SDA Outputs INT/CMPTR Response Time Output Low Voltage -- 1 -- 1 -- -- 4 6 0.8 mA Note 1
tCONV User Programmable V IOL = 4.0 mA -55C TA +125C VDD = 3.3V: TCN75-3.3 MOA, TCN75-3.3 MUA VDD = 5.0V: TCN75-5.0 MOA, TCN75-5.0 MUA
Temp-to-Bits Converter Temperature Accuracy (Note 2) -- 3 -- C
-- tCONV TSET(PU) THYST(PU) Conversion Time TEMP Default Value THYST Default Value -- -- --
0.5 55 80 75
3 -- -- --
C msec C C
25C TA 100C Power-up Power-up
2-Wire Serial Bus Interface VIH VIL VOL CIN ILEAK IOL(SDA) Logic Input High Logic Input Low Logic Output Low Input Capacitance SDA, SCL I/O Leakage SDA Output Low Current VDD x 0.7 -- -- -- -- -- -- -- -- 15 100 -- -- VDD x 0.3 0.4 -- -- 6 V V V pF pA mA (TA = TJ = 25C) IOL = 3 mA
(c) 2006 Microchip Technology Inc.
DS21490C-page 3
TCN75
TCN75 ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: 2.7V VDD 5.5V; -55C (TA = TJ) 125C, CL = 80 pF, unless otherwise noted. Symbol Parameter Min Typ Max Unit Test Conditions
Serial Port Timing fSC tLOW tHIGH tR tF tSU(START) tSC tH(START) tDSU tDH tSU(STOP) tIDLE
Note 1:
Serial Port Frequency Low Clock Period High Clock Period SCL and SDA Rise Time SCL and SDA Fall Time Start Condition Setup Time (for repeated Start Condition) SCL Clock Period Start Condition Hold Time Data in Setup Time to SCL High Data in Hold Time after SCL Low Stop Condition Setup Time Bus Free Time Prior to New Transition
0 1250 1250 -- -- 1250 2.5 100 100 0 100 1250
100 -- -- -- -- -- -- -- -- -- -- --
400 -- -- 250 250 -- -- -- -- -- -- --
kHz nsec nsec nsec nsec nsec sec nsec nsec nsec nsec nsec
Output current should be minimized for best temperature accuracy. Power dissipation within the TCN75 will cause self-heating and temperature drift. At maximum rated output current and saturation voltage, 4 mA and 0.8V, respectively, the error amounts to 0.544C for the SOIC. All part types of the TCN75 will operate properly over the wider power supply range of 2.7V to 5.5V. Each part type is tested and specified for rated accuracy at its nominal supply voltage. As VDD varies from the nominal value, accuracy will degrade 1C/V of VDD change. Human body model, 100 pF discharged through a 1.5k resistor.
2: 3:
TIMING DIAGRAM
tSC SCL
tH (Start) SDA Data In tDSU SDA Data Out tDH
tSU (Stop)
DS21490C-page 4
(c) 2006 Microchip Technology Inc.
TCN75
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Pin Number (8-Pin SOIC) 8-Pin MSOP) 1 2 3 4 5 6 7 8
PIN FUNCTION TABLE
Symbol SDA SCL INT/CMPTR GND A2 A1 A0 VDD Bidirectional Serial Data. Serial Data Clock Input. Interrupt or Comparator Output. System Ground. Address Select Pin (MSB). Address Select Pin. Address Select Pin (LSB). Power Supply Input. Description
(c) 2006 Microchip Technology Inc.
DS21490C-page 5
TCN75
3.0 DETAILED DESCRIPTION
A typical TCN75 hardware connection is shown in Figure 3-1.
+VDD (3V to 5.5V) CBypass 8 A0 Address (Set as Desired) A1 A2 I2CTM Interface SDA SCL 7 6 5 3 0.1 F Recommended Unless Device is Mounted Close to CPU
TCN75
1 2 4
To Controller INT/CMPTR
FIGURE 3-1:
Typical Application
3.1
Serial Data (SDA)
3.4
Address (A2, A1, A0)
Bidirectional. Serial data is transferred in both directions using this pin.
3.2
Serial Clock (SCL)
Input. Clocks data into and out of the TCN75.
Inputs. Sets the three Least Significant bits of the TCN75 8-bit address. A match between the TCN75's address and the address specified in the serial bit stream must be made to initiate communication with the TCN75. Many protocol-compatible devices with other addresses may share the same 2-wire bus.
3.3
INT/CMPTR
3.5
Slave Address
Open Collector, Programmable Polarity. In Comparator mode, unconditionally driven active any time temperature exceeds the value programmed into the TSET register. INT/CMPTR will become inactive when temperature subsequently falls below the THYST setting. (See Section 5.0 "Register Set and Programmer's ModeL", Register Set and Programmer's Model). In Interrupt mode, INT/CMPTR is also made active by TEMP exceeding TSET; it is unconditionally reset to its inactive state by reading any register via the 2-wire bus. If and when temperature falls below THYST, INT/CMPTR is again driven active. Reading any register will clear the THYST interrupt. In Interrupt mode, the INT/CMPTR output is unconditionally reset upon entering Shutdown mode. If programmed as an active-low output, it can be wire-ORed with any number of other open collector devices. Most systems will require a pull-up resistor for this configuration. Note that current sourced from the pull-up resistor causes power dissipation and may cause internal heating of the TCN75. To avoid affecting the accuracy of ambient temperature readings, the pull-up resistor should be made as large as possible. INT/CMPTR's output polarity may be programmed by writing to the INT/CMPTR POLARITY bit in the CONFIG register. The default is active low.
The four Most Significant bits of the Address Byte (A6, A5, A4, A3) are fixed to 1001[B]. The states of A2, A1 and A0 in the serial bit stream must match the states of the A2, A1 and A0 address inputs for the TCN75 to respond with an Acknowledge (indicating the TCN75 is on the bus and ready to accept data). The Slave Address is represented in Table 3-1.
TABLE 3-1:
1 MSB 0
TCN75 SLAVE ADDRESS
0 1 A2 A1 A0 LSBS
DS21490C-page 6
(c) 2006 Microchip Technology Inc.
TCN75
3.6 Comparator/Interrupt Modes
INT/CMPTR behaves differently depending on whether the TCN75 is in Comparator mode or Interrupt mode. Comparator mode is designed for simple thermostatic operation. INT/CMPTR will go active anytime TEMP exceeds TSET. When in Comparator mode, INT/ CMPTR will remain active until TEMP falls below THYST, whereupon it will reset to its inactive state. The state of INT/CMPTR is maintained in Shutdown mode when the TCN75 is in Comparator mode. In Interrupt mode, INT/CMPTR will remain active indefinitely, even if TEMP falls below THYST, until any register is read via the 2-wire bus. Interrupt mode is better suited to interrupt driven microprocessor-based systems. The INT/ CMPTR output may be wire-OR'ed with other interrupt sources in such systems. Note that a pull-up resistor is necessary on this pin since it is an open-drain output. Entering Shutdown mode will unconditionally reset INT/ CMPTR when in Interrupt mode.
(c) 2006 Microchip Technology Inc.
DS21490C-page 7
TCN75
4.0 SHUTDOWN MODE
TABLE 4-1:
Term Transmitter Receiver Master
SERIAL BUS CONVENTIONS
Explanation The device sending data to the bus. The device receiving data from the bus. The device which controls the bus: initiating transfers (Start), generating the clock, and terminating transfers (Stop). The device addressed by the master. A unique condition signaling the beginning of a transfer indicated by SDA falling (High - Low) while SCL is high. A unique condition signaling the end of a transfer indicated by SDA rising (Low - High) while SCL is high. A Receiver acknowledges the receipt of each byte with this unique condition. The Receiver drives SDA low during SCL high of the ACK clock-pulse. The Master provides the clock pulse for the ACK cycle. When the bus is idle, both SDA & SCL will remain high. The state of SDA must remain stable during the High period of SCL in order for a data bit to be considered valid. SDA only changes state while SCL is low during normal data transfers. (See Start and Stop conditions).
When the appropriate bit is set in the configuration register (CONFIG) the TCN75 enters its low-power Shutdown mode (IDD = 1 A, typical) and the temperatureto-digital conversion process is halted. The TCN75's bus interface remains active and TEMP, TSET, and THYST may be read from and written to. Transitions on SDA or SCL due to external bus activity may increase the standby power consumption. If the TCN75 is in Interrupt mode, the state of INT/CMPTR will be reset upon entering Shutdown mode.
Slave Start
4.1
Fault Queue
Stop
To lessen the probability of spurious activation of INT/ CMPTR the TCN75 may be programmed to filter out transient events. This is done by programming the desired value into the Fault Queue. Logic inside the TCN75 will prevent the device from triggering INT/ CMPTR unless the programmed number of sequential temperature-to-digital conversions yield the same qualitative result. In other words, the value reported in TEMP must remain above TSET or below THYST for the consecutive number of cycles programmed in the Fault Queue. Up to a six-cycle "filter" may be selected. See Section 5.0 "Register Set and Programmer's ModeL", Register Set and Programmer's Model.
ACK
NOT Busy Data Valid
4.2
Serial Port Operation
The Serial Clock input (SCL) and bidirectional data port (SDA) form a 2-wire bidirectional serial port for programming and interrogating the TCN75. The following table indicates TCN75 conventions that are used in this bus scheme.
All transfers take place under control of a host, usually a CPU or microcontroller, acting as the Master, which provides the clock signal for all transfers. The TCN75 always operates as a Slave. This serial protocol is illustrated in Figure 5-1. All data transfers have two phases; and all bytes are transferred MSB first. Accesses are initiated by a Start condition, followed by a device address byte and one or more data bytes. The device address byte includes a Read/Write selection bit. Each access must be terminated by a Stop condition. A convention called Acknowledge (ACK) confirms receipt of each byte. Note that SDA can change only during periods when SCL is LOW (SDA changes while SCL is HIGH are reserved for Start and Stop conditions).
4.3
Start Condition (Start)
The TCN75 continuously monitors the SDA and SCL lines for a Start condition (a HIGH-to-LOW transition of SDA while SCL is HIGH), and will not respond until this condition is met.
DS21490C-page 8
(c) 2006 Microchip Technology Inc.
TCN75
4.3.1 ADDRESS BYTE 4.3.4 STOP CONDITION (STOP)
Immediately following the Start condition, the host must next transmit the address byte to the TCN75. The four Most Significant bits of the Address Byte (A6, A5, A4, A3) are fixed to 1001(B). The states of A2, A1 and A0 in the serial bit stream must match the states of the A2, A1 and A0 address inputs for the TCN75 to respond with an Acknowledge (indicating the TCN75 is on the bus and ready to accept data). The eighth bit in the Address Byte is a Read/Write Bit. This bit is a `1' for a read operation or `0' for a write operation. Communications must be terminated by a Stop condition (a LOW-to-HIGH transition of SDA while SCL is HIGH). The Stop condition must be communicated by the transmitter to the TCN75.
4.3.5
POWER SUPPLY
4.3.2
ACKNOWLEDGE (ACK)
Acknowledge (ACK) provides a positive handshake between the host and the TCN75. The host releases SDA after transmitting eight bits then generates a ninth clock cycle to allow the TCN75 to pull the SDA line LOW to acknowledge that it successfully received the previous eight bits of data or address.
To minimize temperature measurement error, the TCN75-3.3 MOA and TCN75-3.3 MUA are factory calibrated at a supply voltage of 3.3V 5% and the TCN75-5.0 MOA and TCN75-5.0 MUA are factory calibrated at a supply voltage of 5V 5%. Either device is fully operational over the power supply voltage range of 2.7V to 5.5V, but with a lower measurement accuracy. The typical value of this power supply-related error is 2C.
4.3.3
DATA BYTE
After a successful ACK of the address byte, the host must next transmit the data byte to be written or clock out the data to be read. (See the appropriate timing diagrams.) ACK will be generated after a successful write of a data byte into the TCN75.
(c) 2006 Microchip Technology Inc.
DS21490C-page 9
TCN75
5.0 REGISTER SET AND PROGRAMMER'S MODEL
REGISTER (POINT), 8 BITS, WRITE ONLY
D[5] D[4] D[3] D[2] D[1] D[0] Pointer D3 - D4: Fault Queue: Number of sequential temperature-to-digital conversions with the same result before the INT/CMPTR output is updated: D4 0 0 1 Register Selection Via the Pointer Register D1 0 0 1 1 D0 0 1 0 1 Register Selection TEMP CONFIG THYST TSET 1 D3 0 1 0 1 Number of Conversions 1 (Power-up default) 2 4 6
TABLE 5-1:
D[7] D[6]
Must Be Set To Zero
TABLE 5-2:
CONFIGURATION REGISTER (CONFIG), 8 BITS, READ/ WRITE
D [4] D [3] D [2] INT/ CMPTR, Polarity D [1] COM P/INT D [0] Shutdown
D [7]
D [6]
D [5]
Must Be Set To Zero
Fault Queue
D0: Shutdown: 0 = Normal Operation 1 = Shutdown Mode D1: CMPTR/INT: 0 = Comparator Mode 1 = Interrupt Mode D2: INT/CMPTR POLARITY: 0 = Active Low 1 = Active High
DS21490C-page 10
(c) 2006 Microchip Technology Inc.
TCN75
TABLE 5-3:
D[15] MSB D[14] D7
TEMPERATURE (TEMP) REGISTER, 16 BITS, READ ONLY
D[13] D6 D[12] D5 D[11] D4 D[10] D3 D[9] D2 D[8] D1 D[7] LSB D[6] X D[5] X D[4] X D[3] X D[2] D[1] X X D[0] X
The binary value in this register represents ambient temperature following a conversion cycle.
TABLE 5-4:
D[15] MSB D[14] D7
TEMPERATURE SET POINT (TSET) REGISTER, 16 BITS, READ/WRITE
D[13] D6 D[12] D5 D[11] D4 D[10] D3 D[9] D2 D[8] D1 D[7] LSB D[6] X D[5] X D[4] X D[3] X D[2] D[1] X X D[0] X
TABLE 5-5:
D[15] MSB D[14] D7
HYSTERESIS (THYST) REGISTER, 16 BITS, READ/WRITE
D[13] D6 D[12] D5 D[11] D4 D[10] D3 D[9] D2 D[8] D1 D[7] LSB D[6] X D[5] X D[4] X D[3] X D[2] D[1] X X D[0] X
In the TEMP, TSET, and THYST registers, each unit value represents one-half degree (Celsius). The value is in 2's - complement binary format such that a reading of 000000000b corresponds to 0C. Examples of this temperature to binary value relationship are shown in Table 5-6.
TABLE 5-6:
Temperature +125C +25C +0.5C 0C 0.5C -25C -40C -55C
TEMPERATURE TO DIGITAL VALUE CONVERSION
Binary Value 0 11111010 0 00110010 0 00000001 0 00000000 1 11111111 1 11001110 1 10110000 1 10010010 HEX Value 0FA 032 001 00 1FF 1CE 1B0 192
TABLE 5-7:
Name TEMP TSET THYST POINT CONFIG
TCN75'S REGISTER SET SUMMARY
Description Ambient Temperature Temperature Setpoint Temperature Hysteresis Register Pointer Configuration Register Width 16 16 16 8 8 Read X X X X X X X X X Write Notes 2's Complement Format 2's Complement Format 2's Complement Format
(c) 2006 Microchip Technology Inc.
DS21490C-page 11
TCN75
1 9 1 9 1 9
1 Start by Master
0
0
1 A2 A1 A0 R/W Ack by
D7 D6 D5 D4 D3 D2 D1 D0 Most Significant Data Byte
D7 D6 D5 D4 D3 D2 D1 D0
Address Byte
TCN75
1 9 1
Ack Least Significant Data Byte by Master 9 .....
Stop No Ack Cond by by Master Master
(a) Typical 2-Byte Read From Preset Pointer Location Such as Temp, TOS, THYST
1 Start by Master
0
0
1 A2 A1 A0 R/W Ack by
0
0
0
0
0
0 D1 D0 Ack by
.....
Address Byte 1
Pointer Byte 9 1
TCN75
TCN75
9
1
9
1 Repeat Start by Master
0
0
1 A2 A1 A0 R/W Ack by
D7 D6 D5 D4 D3 D2 D1 D0 Most Significant Data Byte
D7 D6 D5 D4 D3 D2 D1 D0
Address Byte
TCN75
Ack Least Significant Data Byte by Master
Stop No Ack Cond by by Master Master
(b) Typical Pointer Set Followed by Immediate Read for 2-Byte Register Such as Temp, TOS, THYST 1 9 1 9
1 Start by Master
0
0
1 A2 A1 A0 R/W Ack by
D7 D6 D5 D4 D3 D2 D1 D0 Data Byte
Address Byte
TCN75T
Stop No Ack Cond by by Master Master
(c) Typical 1-Byte Read From Configuration Register with Preset Pointer
FIGURE 5-1:
Timing Diagrams
DS21490C-page 12
(c) 2006 Microchip Technology Inc.
(c) 2006 Microchip Technology Inc.
1 9 1 9 1 9
1
9
Timing Diagrams (Continued)
1 0 A2 A1 A0 R/W Ack by Ack by Address Byte 0 0 0 0 0 0 D0 1 0 0 1
0
0
1 A2 A1 A0 R/W
D7 D6 D5 D4 D3 D2 D1 D0 Data Byte Stop No Ack Cond by by Master Master
Start by Master
Ack Repeat Address Byte Pointer Byte by Start TCN75 TCN75 by Master (d) Typical Pointer Set Followed by Immediate Read from Configuration Register
TCN75
9
1 9 1 9 1
1 0 Ack by Pointer Byte Ack by Configuration Byte 0 0 0 0 0 D1 D0 0 0
0
0
1 A2 A1 A0 R/W
0 D4 D3 D2 D1 D0 Ack by
Start by Master
Address Byte
TCN75T TCN75
9 1 9 1
TCN75
9 1
Stop Cond by Master
(e) Configuration Register Write 9
1
1 0 Ack by Pointer Byte 0 0 0 0 0 D1 D0
0
0
1 A2 A1 A0 R/W
D7 D6 D5 D4 D3 D2 D1 D0 Most Significant Data Byte Ack by
D7 D6 D5 D4 D3 D2 D1 D0 Least Significant Data Byte Ack by Stop Cond by Master
Start by Master
Address Byte
Ack by
TCN75
TCN75
TCN75
TCN75
(f) TOS and THYST Write
DS21490C-page 13
TCN75
TCN75
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
Package marking data not available at this time.
6.2
Taping Form
Component Taping Orientation for 8-Pin MSOP Devices
User Direction of Feed
Pin 1
W
P Standard Reel Component Orientation for 713 Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
8-Pin MSOP
12 mm
8 mm
2500
13 in
Component Taping Orientation for 8-Pin SOIC (Narrow) Devices
User Direction of Feed
Pin1
W
P Standard Reel Component Orientation for 713 Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
8-Pin SOIC (N)
12 mm
8 mm
2500
13 in
DS21490C-page 14
(c) 2006 Microchip Technology Inc.
TCN75
6.3 Package Dimensions
8-Pin MSOP
Pin 1
.122 (3.10) .197 (5.00) .114 (2.90) .189 (4.80)
.026 (0.65) Typ.
.122 (3.10) .114 (2.90) .043 (1.10) Max. .016 (0.40) .010 (0.25) .002 (0.05) .006 (0.15)
6 Max. .028 (0.70) .016 (0.40)
.008 (0.20) .005 (0.13)
Dimensions: inches (mm)
8-Pin SOIC
Pin 1
.157 (3.99) .150 (3.81)
.244 (6.20) .228 (5.79)
.050 (1.27) Typ.
.197 (5.00) .189 (4.80) .069 (1.75) .053 (1.35) .020 (0.51) .010 (0.25) .013 (0.33) .004 (0.10) .010 (0.25) .007 (0.18) .050 (1.27) .016 (0.40) Dimensions: inches (mm)
8 Max.
(c) 2006 Microchip Technology Inc.
DS21490C-page 15
TCN75
NOTES:
DS21490C-page 16
(c) 2006 Microchip Technology Inc.
TCN75
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DS21490C-page 17
TCN75
READER RESPONSE
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From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: TCN75 Questions: 1. What are the best features of this document? Y N Literature Number: DS21490C FAX: (______) _________ - _________
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DS21490C-page 18
(c) 2006 Microchip Technology Inc.
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* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
(c) 2006 Microchip Technology Inc.
DS21490C-page 19
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8676-6200 Fax: 86-28-8676-6599 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256
ASIA/PACIFIC
India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-5160-8631 Fax: 91-11-5160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
02/16/06
DS21490C-page 20
(c) 2006 Microchip Technology Inc.

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